Design Verification Engineer
Due to the classified nature of the work the candidate will be required to work on-site at a location housing Common Engineering / Classified Environment (CECE) facilities. Such locations include: NH - Nashua / Merrimack / Manchester; MA - Burlington; NJ - Totowa; VA - Manassas, Arlington; TX - Austin; CA - San Diego
A design verification engineer is needed to perform DV planning, develop testbench infrastructure (environment, stimulus generators, monitors, predictors, checkers), develop testcases. run simulations, and assist with the diagnosis of functional issues found during simulations. The candidate will work with requirements and design documentation as well as the design team to understand design intent and implementation, and to assist in the debug of issues found during simulation. The candidate may work as part of a larger DV team, or may be the sole DV engineer on the project.
Requires minimum 8 years experience developing VHDL or SystemVerilog / UVM code for verification.
Requires at least ten (10) years of work experience. Requires at least eight (8) years of hands-on work doing design verification.
Experience using Git source code management tool Experience using Siemens/Mentor QuestaSim tools. Experience with Atlassian tools (JIRA, Bitbucket) Experience using Makefiles Experience with scripting languages (TCL, Python, Perl, etc) Ability to read and understand RTL code implemented in VHDL
Experience working in the defense industry. Experience working in the development of EW systems.
Meet Your Recruiter
Client Relationship Coordinator
Marques joined The Panther Group in 2015. He developed a keen eye for talent which serves both our candidates and clients well!
Fun Fact: He is a big Boston sports fan, and is a season ticket holder for the New England Patriots.